The present invention relates to substrates and semiconductor packages with the substrates, and more particularly, to a substrate for preventing delamination between the substrate and a chip mounted on the substrate.
As shown in FIGS. 3(A) and 3(B), a conventional substrate 10 for use with a BGA (ball grid array) semiconductor package is formed with a chip attach area 11, and a metal layer (usually copper) is applied over the chip attach area 11; the metal layer completely covers the chip attach area 11, and is therefore designated by the same reference numeral 11. A solder mask layer 12 is then applied over the substrate 10 and the metal layer 11, and formed with a plurality of openings 13 for allowing a portion of the metal layer 11 to be exposed. For mounting a chip (not shown) on the substrate 10, an adhesive (not shown) is spread over the chip attach area 11 to fill into the openings 13 and to be attached to the solder mask layer 12 and the exposed portion of the metal layer 11, such that the chip can be bonded to the substrate 10 by means of the adhesive. However, the above structure has significant drawbacks. First, with the chip attach area 11 being entirely covered by the metal layer 11, the solder mask layer 12 applied over the metal layer 11 may be easily subject to delamination at interface between the solder mask layer 12 and the metal layer 11 due to weak adhesion between solder mask and metal materials. Moreover, the adhesive for chip bonding is attached to the metal layer 11 and the solder mask layer 12; however, due to weak adhesion between adhesive and metal materials, delamination may occur at interface between the adhesive and the metal layer 11, and further extend to interface between the adhesive and the solder mask layer 12, thereby severely damaging bonding between the chip and the substrate 10.
Therefore, U.S. Pat. Nos. 5,703,402 and 5,801,440 disclose another BGA substrate 20 illustrated in FIGS. 4(A) and 4(B). As shown in FIG. 4(A), this substrate 20 is characterized by forming a metal layer 22 of a sunray shape without entirely covering a chip attach area 21 on the substrate 20. A solder mask layer 23 is applied over the substrate 20 and the metal layer 22, and formed with a plurality of openings 24 for allowing a portion of the metal layer 22 to be exposed. As part of the chip attach area 21 of the substrate 20 is uncovered by the sunray-shaped metal layer 22, the solder mask layer 23 can be directly attached to the uncovered part of the chip attach area 21, which increases bonding between the solder mask layer 23 and the substrate 20 due to relatively strong adhesion between solder mask and substrate materials, thereby helping prevent delamination problems from occurrence. However, when an adhesive (not shown) for chip-bonding use is applied over the chip attach area 21 of the substrate 20, the adhesive is still attached to the solder mask layer 23 and the exposed portion of the metal layer 22, without resolving the drawback of delamination at adhesive-substrate interface as described above for the previous conventional substrate 10.
Therefore, the problem to be solved is to provide a substrate for improving adhesion between an adhesive and the substrate and for assuring bonding of a chip to the substrate.
An objective of the present invention is to provide a delamination-preventing substrate and a semiconductor package with the same, so as to enhance bonding between the substrate and a chip mounted on the substrate.
Another objective of the invention is to provide a delamination-preventing substrate and a semiconductor package with the same, so as to effectively reduce stress generated between the substrate and a chip mounted on the substrate.
A further objective of the invention is to provide a delamination-preventing substrate and a semiconductor package with the same, so as to prevent delamination at interface between the substrate and a chip mounted on the substrate.
In accordance with the above and other objectives, the present invention proposes a delamination-preventing substrate and a semiconductor package with the substrate. The semiconductor package comprises: a substrate having a first surface and a second surface opposed to the first surface, the first surface being formed with a chip attach area that is covered by a metal layer thereon, wherein a solder mask layer is applied over the metal layer and the first surface of the substrate, and formed with a plurality of first openings corresponding in position to the metal layer, allowing a portion of the metal layer to be exposed to the first openings, and the exposed portion of the metal layer is formed with a plurality of second openings respectively within the first openings, so as to partly expose the first surface of the substrate to the second openings; at least a chip having a first surface and a second surface opposed to the first surface, wherein the second surface of the chip is attached to the chip attach area on the first surface of the substrate; an adhesive layer for attaching the second surface of the chip to the chip attach area of the substrate, wherein the adhesive layer fills into the first and second openings to be in contact with the exposed part of the first surface of the substrate; a plurality of bonding wires bonded to the first surface of the chip and to the first surface, outside the chip attach area, of the substrate, so as to electrical connect the chip to the substrate by means of the bonding wires; an encapsulant formed on the first surface of the substrate for encapsulating the chip and the bonding wires; and a plurality of solder bumps implanted on the second surface of the substrate for electrically connecting the chip to an external device.
The metal layer on the substrate is of a sunray shape, and partly covers the chip attach area, such that the solder mask layer can be directly attached to uncovered part of the chip attach area, so as to increase bonding between the solder mask layer and the substrate. Moreover, with the forming of the first and second openings, the adhesive layer is adapted to be in direct contact with exposed part of the first surface of the substrate; this is the characteristic feature of the invention. This structural arrangement is used to reduce contact area between the adhesive layer and the metal layer, and increase contact area between the adhesive layer and the substrate. As adhesion between adhesive and substrate materials is stronger than adhesion between adhesive and metal materials, direct contact between the adhesive layer and the substrate helps enhance bonding between the chip and the substrate, without easily subject to delamination at chip-substrate interface as in the prior art. Further due to direct contact between the adhesive layer and the substrate, the adhesive layer can help reduce stress generated between the chip and the substrate, so as to prevent stress-induced delamination from occurrence.